The cRIO-EVR prototype is based in FPGA technology from Lattice Semiconductor.

CompactRIO Event Receiver prototype

The prototype hardware platform provides:

• SFP transceiver for event link
• Lattice ECP2M-20 FPGA with high speed serial link
• 10/100 ethernet for control and configuration
• 64 Mbytes of DDR2 memory
• 2 × 16 Mbits serial flash memory
• EEPROM
• 9 to 35 VDC power supply input

There is currently work going on to port the RTEMS operating system to the Lattice Mico32 target that can be implemented inside the FPGA.